A Bu er-Oriented Methodology for Microarchitecture Validation
نویسندگان
چکیده
We propose a methodology for validating microarchitecture speciications. We view microarchitecture features as speciic operations on entries of various buuers in the processor. Our validation approach is to determine the functionality of a buuer type, model its operations at the microarchitecture level using abstract nite state machine (FSM) models, and rigorously generate instruction sequences that systematically exercise the model of each instance of that buuer type. A high-level test sequence is derived based on the abstract FSM model using FSM testing techniques, and then translated to a test program that exercises the functionality of each buuer entry. This methodology is applied to the microarchitecture speciications of the PowerPC 604. The eeectiveness of the sequences generated using our methodology is compared with that of some real and randomly-generated programs. Simulation results show that all targeted FSM transitions are covered by our sequences with 1000X and at least 3X fewer instructions than real and randomly-generated programs, respectively.
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